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M48Z09 M48Z19
CMOS 8K x 8 ZEROPOWER SRAM
INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY UNLIMITED WRITE CYCLES READ CYCLE TIME EQUALS WRITE CYCLE TIME AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION POWER-FAIL INTERRUPT CHOICE of TWO WRITE PROTECT VOLTAGES: - M48Z09: 4.5V VPFD 4.75V - M48Z19: 4.2V VPFD 4.5V SELF CONTAINED BATTERY in the CAPHAT DIP PACKAGE 11 YEARS of DATA RETENTION in the ABSENCE of POWER PIN and FUNCTION COMPATIBLE with the MK48Z09, 19 and JEDEC STANDARD 8K x 8 SRAMs DESCRIPTION The M48Z09,19 ZEROPOWER(R) RAM is an 8K x 8 non-volatile static RAM which is pin and function compatible with the MK48Z09,19. A special 28 pin 600mil DIP CAPHATTM package houses the M48Z09,19 silicon with a long life lithium button cell to form a highly integrated battery backed-up memory solution. Table 1. Signal Names
E1
A0-A12 DQ0-DQ7 INT E1 E2 G W VCC VSS November 1994 Address Inputs Data Inputs / Outputs Power Fail Interrupt Chip Enable 1 Chip Enable 2 Output Enable Write Enable Supply Voltage Ground 1/13
28 1
PCDIP28 (PC) Battery CAPHAT
Figure 1. Logic Diagram
VCC
13 A0-A12
8 DQ0-DQ7
W M48Z09 M48Z19 INT
E2 G
VSS
AI01184
M48Z09, M48Z19
Table 2. Absolute Maximum Ratings
Symbol TA TSTG VIO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off) Input or Output Voltages Supply Voltage Output Current Power Dissipation Value 0 to 70 -40 to 85 -0.3 to 7 -0.3 to 7 20 1 Unit C C V V mA W
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability. CAUTION: Negative undershoots below -0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Mode Deselect Deselect Write Read Read Deselect Deselect
Note: X = VIH or VIL
VCC
E1 VIH
E2 X VIL VIH VIH VIH X X
G X X X VIL VIH X X
W X X VIL VIH VIH X X
DQ0-DQ7 High Z High Z DIN DOUT High Z High Z High Z
Power Standby Standby Active Active Active CMOS Standby Battery Back-up Mode
4.75V to 5.5V or 4.5V to 5.5V
X VIL VIL VIL
VSO to VPFD (min) VSO
X X
Figure 2A. DIP Pin Connections
DESCRIPTION (cont'd) The M48Z09,19 button cell has sufficient capacity and storage life to maintain data for an accumulated time period of at least 11 years in the absence of power over the operating temperature range. The M48Z09,19 is a non-volatile pin and function equivalent to any JEDEC standard 8K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The M48Z09,19 also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data and clock operation until valid power returns.
INT A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
28 1 27 2 26 3 25 4 24 5 23 6 7 M48Z09 22 M49Z19 21 8 20 9 19 10 18 11 17 12 13 16 14 15
AI01185
VCC W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3
2/13
M48Z09, M48Z19
Figure 3. Block Diagram
A0-A12
DQ0-DQ7 LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY POWER 8K x 8 SRAM ARRAY E1 VPFD E2 W G
VCC
INT
VSS
AI01397
READ MODE The M48Z09,19 is in the Read Mode whenever W (Write Enable) is high, E1 (Chip Enable 1) is low, and E2 (Chip Enable 2) is high. The device architecture allows ripple- through access of data from eight of 65,536 locations in the static storage array. Thus, the unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within tAVQV (Address Access Time) after the last address input signal is stable, providing that the E1, E2, and G access times are also satisfied. If the E1, E2 and G access times are not met, valid data will be available after the latter of the Chip Enable Access Times (tE1LQV or tE2HQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E1, E2 and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E1, E2 and G remain active, output data will remain valid for tAXQX (Output Data Hold Time) but will go indeterminate until the next Address Access.
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V
Note that Output Hi-Z is defined as the point where data is no longer driven.
Figure 4. AC Testing Load Circuit
5V
1.8k DEVICE UNDER TEST 1k
OUT
CL = 100pF or 30pF
CL includes JIG capacitance
AI01398
3/13
M48Z09, M48Z19
Table 4. Capacitance (1) (TA = 25 C)
Symbol CIN CIO
(2)
Parameter Input Capacitance Input / Output Capacitance
Test Condition VIN = 0V VOUT = 0V
Min
Max 10 10
Unit pF pF
Notes: 1. Effective capacitance calculated from the equation C = It/V with V = 3V and power supply at 5V. 2. Outputs deselected
Table 5. DC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol ILI ILO ICC ICC1 ICC2 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage (INT) Output High Voltage
(1)
Test Condition 0V VIN VCC 0V VOUT VCC Outputs open E1 = VIH, E2 = VIL E1 = VCC - 0.2V, E2 = VSS + 0.2V
Min
Max 1 5 80 3 3
Unit A A mA mA mA V V V V V
-0.3 2.2 IOL = 2.1mA IOL = 0.5mA IOH = -1mA 2.4
0.8 VCC + 0.3 0.4 0.4
Note: 1. The INT pin is Open Drain.
Table 6. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70C)
Symbol VPFD VPFD VSO tDR Parameter Power-fail Deselect Voltage (M48Z09) Power-fail Deselect Voltage (M48Z19) Battery Back-up Switchover Voltage Expected Data Retention Time 11 Min 4.5 4.2 Typ 4.6 4.3 3.0 Max 4.75 4.5 Unit V V V YEARS
Note: 1. All voltages referenced to VSS.
4/13
M48Z09, M48Z19
Table 7. Power Down/Up Mode AC Characteristics (TA = 0 to 70C)
Symbol tPD tF
(1)
Parameter E1 or W at VIH or E2 at VIL before Power Down VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSO VCC Fall Time VPFD(min) to VPFD (max) VCC Rise Time VSO to VPFD (min) VCC Rise Time E1 or W at VIH or E2 at VIL after Power Up INT Low to Auto Deselect VPFD (max) to INT High
Min 0 300 10 0 1 1 10
Max
Unit s s s s s ms
tFB (2) tR tRB tREC tPFX
(3) tPFH
40 120
s s
Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). 2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data. 3. INT may go high anytime after VCC exceeds VPFD (min) and is guaranteed to go high tPFH after VCC exceeds VPFD (max).
Figure 5. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tPD tFB tPFX INT tREC INPUTS
RECOGNIZED
tDR tRB
tR
tPFH
DON'T CARE
NOTE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI00566
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E1 high or E2 low as VCC rises past VPFD(min). Some systems may performs inadvertent write cycles after VCC rises above VPFD(min) but before normal system operations begins. Even though a power on reset is being applied to the processor a reset condition may not occur until after the system clock is running.
5/13
M48Z09, M48Z19
Table 8. Read Mode AC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z09 / 19 Symbol Parameter Min tAVAV tAVQV tE1LQV tE2HQV tGLQV
(1) (1) (1)
-100 Max
Unit
Read Cycle Time Address Valid to Output Valid Chip Enable 1 Low to Output Valid Chip Enable 2 High to Output Valid Output Enable Low to Output Valid Chip Enable 1 Low to Output Transition Chip Enable 2 High to Output Transition Output Enable Low to Output Transition Chip Enable 1 High to Output Hi-Z Chip Enable 2 Low to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
100 100 100 100 50 10 10 5 50 50 40 5
ns ns ns ns ns ns ns ns ns ns ns ns
(1)
tE1LQX (2) tE2HQX tGLQX tE1HQZ tE2LQZ tGHQZ tAXQX
(2)
(2) (2) (2) (2) (1)
Notes: 1. CL= 100pF (see Figure 4). 2. CL= 30pF (see Figure 4)
Figure 6. Read Mode AC Waveforms
tAVAV A0-A12 tAVQV tE1LQV E1 tE1LQX tE2HQV E2 tE2HQX tGLQV G tGLQX DQ0-DQ7 VALID
AI00962
VALID tAXQX tE1HQZ
tE2LQZ
tGHQZ
6/13
M48Z09, M48Z19
Table 9. Write Mode AC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z09 / 19 Symbol Parameter Min tAVAV tAVWL tAVE1L tAVE2H tWLWH tE1LE1H tE2HE2L tWHAX tE1HAX tE2LAX tDVWH tDVE1H tDVE2L tWHDX tE1HDX tE2LDX tWLQZ
(1, 2)
-100 Max
Unit
Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable 1 Low Address Valid to Chip Enable 2 High Write Enable Pulse Width Chip Enable 1 Low to Chip Enable 1 High Chip Enable 2 High to Chip Enable 2 Low Write Enable High to Address Transition Chip Enable 1 High to Address Transition Chip Enable 2 Low to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable 1 High Input Valid to Chip Enable 2 Low Write Enable High to Input Transition Chip Enable 1 High to Input Transition Chip Enable 2 Low to Input Transition Write Enable Low to Output Hi-Z Address Valid to Write Enable High Address Valid to Chip Enable 1 High Address Valid to Chip Enable 2 Low Write Enable High to Output Transition
100 0 0 0 80 80 80 10 10 10 50 50 50 5 5 5 50 80 80 80 10
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tAVWH tAVE1H tAVE2L tWHQX
(1, 2)
Notes: 1. CL= 30pF (see Figure 4). 2. If E1 goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance state.
7/13
M48Z09, M48Z19
Figure 7. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A12 VALID tAVWH tAVE1L E1 tAVE2H E2 tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI00963
tWHAX
tWHQX
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A12 VALID tAVE1H tAVE1L E1 tE1LE1H tE1HAX
tAVE2L tAVE2H E2 tAVWL W tE1HDX tE2LDX DQ0-DQ7 DATA INPUT tDVE1H tDVE2L tE2HE2L tE2LAX
AI00964B
8/13
M48Z09, M48Z19
WRITE MODE The M48Z09,19 is in the Write Mode whenever W, E1, and E2 are active. The start of a write is referenced from the latter occurring falling edge of W or E1, or the rising edge of E2. A write is terminated by the earlier rising edge of W or E1, or the falling edge of E2. The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low for minimum of tE1HAX or tE2LAX from Chip Enable or tWHAX from Write Enable prior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E1 and G and a high on E2, a low on W will disable the outputs tWLQZ after W falls. DATA RETENTION MODE With valid VCC applied, the M48Z09,19 operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD(max), VPFD(min) window. All outputs become high impedance, and all inputs are treated as "don't care." Note: A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD(min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48Z09,19 may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48Z09,19 for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD(min). E1 should be kept high or E2 low as VCC rises past VPFD(min) to prevent inadvertent write cycles prior to processor stabilization. Normal RAM operation can resume tREC after VCC exceeds VPFD(max). POWER FAIL INTERRUPT PIN The M48Z09,19 continuously monitors VCC. When VCC falls to the power-fail detect trip point, an interrupt is immediately generated. An internal clock provides a delay of between 10s and 40s before automatically deselecting the M48Z09,19. The INT pin is an open drain output and requires an external pull up resistor, even if the interrupt output function is not being used. SYSTEM BATTERY LIFE The useful life of the battery in the M48Z09,19 is expected to ultimately come to an end for one of two reasons: either because it has been discharged while providing current to the RAM in the battery back-up mode, or because the effects of aging render the cell useless before it can actually be completely discharged. The two effects are virtually unrelated allowing discharge, or Capacity Consumption, and the effects of aging, or Storage Life, to be treated as two independent but simultaneous mechanisms. The earlier occurring failure mechanism defines the battery system life of the M48Z09,19. Cell Storage Life Storage life is primarily a function of temperature. Figure 9 illustrates the approximate storage life of the M48Z09,19 battery over temperature. The results in Figure 9 are derived from temperature accelerated life test studies performed at SGSTHOMSON. For the purpose of the testing, a cell failure is defined as the inability of a cell stabilized at 25C to produce a 2.4V closed circuit voltage across a 250 k load resistor. The two lines, t1% and t50%, represent different failure rate distributions for the cell's storage life. At 70C, for example, the t1% line indicates that an M48Z09,19 has a 1% chance of having a battery failure 28 years into its life while the t50% shows the part has a 50% chance of failure at the 50 year mark. The t1% line represents the practical onset of wear out and can be considered the worst case Storage Life for the cell. The t50% can be considered the normal or average life.
9/13
M48Z09, M48Z19
Calculating Storage Life The following formula can be used to predict storage life:
1 {[(TA1/TT)/SL1]+[(TA2/TT)/SL2]+...+[(TAN/TT)/SLN]}
Predicted storage life
1 {[(8322/8760)/200]+[(431/8760)/28]}
where, - TA1, TA2, TAN = time at ambient temperature 1, 2, etc. - TT = total time = TA1+TA2+...+TAN - SL1, SL2, SLN = storage life at temperature 1, 2, etc. For example an M48Z09,19 is exposed to temperatures of 55C or less for 8322 hrs/yr, and temperatures greater than 60C but less than 70C for the remaining 438 hrs/yr. Reading predicted t1% values from Figure 9, - SL1 200 yrs, SL2 = 28 yrs - TT = 8760 hrs/yr - TA1 = 8322 hrs/yr, TA2 = 438 hrs/yr
or 154 years. As can be seen from these calculations and the results, the expected life time of the M48Z09, 19 should exceed most system requirements. Estimated System Life Since either storage life or capacity consumption can end the battery's life, the system life is marked by which ever occurs first. Reference for System Life Each M48Z09,19 is marked with a nine digit manufacturing date code in the form of H99XXYYZZ. For example, H995B9431 is: H = fabricated in Carrollton, TX 9 = assembled in Muar, Malaysia, 9 = tested in Muar, Malaysia, 5B = lot designator, 9431 = assembled in the year 1994, work week 31.
Figure 9. Predicted Battery Storage Life versus Temperature
AI01399
50 40 30 20 t1% t50% (AVERAGE)
10
YEARS
8 6 5 4 3 2
1 20 30 40 50 60 70 80 90
TEMPERATURE (Degrees Celsius)
10/13
M48Z09, M48Z19
ORDERING INFORMATION SCHEME
Example:
M48Z09
-100 PC
1
Supply Voltage and Write Protect Voltage 09 19 VCC = 4.75V to 5.5V VPFD = 4.5V to 4.75V VCC = 4.5V to 5.5V VPFD = 4.2V to 4.5V -100
Speed 100ns PC
Package PCDIP28
Temp. Range 1 0 to 70 C
For a list of available options (Supply Voltage, Speed, Package, etc...) refer to the current Memory Shortform catalogue. For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you.
11/13
M48Z09, M48Z19
PCDIP28 - 28 pin Plastic DIP, battery CAPHAT
mm Typ A A1 A2 B B1 C D E e1 e3 eA L N
PCDIP28
Symb
inches Max 9.65 0.76 8.89 0.53 1.78 0.31 39.88 18.34 2.79 36.32 16.00 3.81 Typ Min 0.350 0.015 0.330 0.015 0.045 0.008 1.550 0.702 0.090 1.170 0.600 0.120 28 Max 0.380 0.030 0.350 0.021 0.070 0.012 1.570 0.722 0.110 1.430 0.630 0.150
Min 8.89 0.38 8.38 0.38 1.14 0.20 39.37 17.83 2.29 29.72 15.24 3.05 28
A2
A
A1 B1 B e3 D
N
L eA
C
e1
E
1 PCDIP
Drawing is not to scale
12/13
M48Z09, M48Z19
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved (R) ZEROPOWER is a registered trademark of SGS-THOMSON Microelectronics TM CAPHAT and BYTEWIDE are trademarks of SGS-THOMSON Microelectronics SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
13/13

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